ΔΣAD modulator for low power application

This paper proposes a new architecture of the feedforward multibit ΔΣAD modulator for low power application. The SQNDR (Signal to Quantization Noise and Distortion Ratio) of ΔΣAD modulator is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. In a full feedforward ΔΣAD modulator structure, the signal swings through the loop filter is smaller than a feedbackΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter of the feedforward structure can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. However, in conventional feedforwardΔΣAD modulator, an analog adder is needed before the quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, firstly, we propose a new architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. Furthermore, we extend the architecture with noiseshaping enhancement, the modulator contains a second-order loop filter can deliver a third-order noise-shaping. We conducted MATLAB simulations to validate the proposed architecture.